1. Field of the Invention
The present invention relates to a method for controlling a peak current, and more particularly to a method for controlling a peak current generated by a plurality of registers in a circuit.
2. Description of Related Art
In current Very Large Scale Integrated (VLSI) Circuits, in order to propagate a clock signal to each clock register nearly at the same time, the most common method is to connect the clock buffers in a series, and this structure is generally called a clock tree. As for the operation of the clock tree, the clock signal periodically charges and discharges the capacitor at each output terminal of the clock tree, which is significantly different from the common combinational logic that changes the voltage level of the output terminal only according to the logic function.
As for a sequential circuit, the peak current may be divided into three parts, namely, synchronous logic, clock tree and combinational logic. Through a further analysis, the synchronous logic and the clock tree parts are both triggered and driven by a clock signal. In the design of zero clock skew circuit, the clock signal reaches each register simultaneously, such that the current generated by all the registers accumulate at the same time, thus causing a huge peak current. Particularly, along with the progress of the manufacturing process technology, the design complexity is raised, and the number of the registers is increased accordingly, thus, the peak current effect becomes more obvious. Conventionally, the common method for reducing the peak current on the chip is to use a clock tree structure with non-zero clock skew. This structure uses reaching times of different clock signals to properly adjust the triggering time of the synchronous logic, such that the current consumption of individual synchronous logics are staggered, thus reducing the peak current. Or otherwise, a clock tree structure for selectively enabling clock signals may be used, which mainly disables one part of clock signals that do not operate temporarily in the sequential circuit, so as to reduce the unnecessary dynamic power consumption, thus reducing the power consumption of the whole chip.